A TDCAM cell structure in a ternary dynamic content addressable memory (TDCAM) is described in, for example, ‘Records of the 2000 IEEE International Workshop on Memory Technology, Design and Testing, 2000, Page(s): 101-105’ (hereinafter, called “Literature 1”).
One example of a cell structure shown in FIG. 2 in Literature 1 is shown in FIG. 21.
The cell is formed utilizing an Embedded DRAM (dynamic random access memory) processing technique, and it has a memory function storing ternary data utilizing NMOS (N-channel metal oxide semiconductor) transistors T1 and T2, and capacitors C1 and C2.
Further, the cell has an XNOR (Exclusive NOR) operation function configured of NMOS transistors T3, T4, T5, T6, and it performs comparison between stored data (entry) and inputted data. Incidentally, a VPLT is a so-called “plate electrode voltage” inputted one of electrodes of the capacitors C1, C2.
The memory function will be first explained.
The ternary data is data ‘1’ state, data ‘0’ state, and data ‘X’ representing so-called ‘Don't care’ state. When high voltage is defined as logic ‘1’ and low voltage is defined as logic ‘0’, a logical value of the storage node (N1, N2) is (1, 0) in case of the data ‘1’, it is (0, 1) in case of data ‘0’, and it is (0,0) in case of data ‘X’.
Refresh operation of stored data is performed through the transistors T1, T2. Though omitted in FIG. 21, read and rewrite operations are performed using sense amplifiers respectively connected to bit lines BL1, BL2.
The XNOR operation function will be then explained.
Data compared with stored data in search operation is ternary data inputted via search lines SL1, SL2. Breakdown of the ternary data includes data ‘1’, data ‘0’ and data ‘X’ representing a so-called ‘MASK’ state.
When the entry and the inputted data are the same, namely, when they match with each other, since connection of a match line ML precharged to a high voltage and a discharge line DCL fixed to a low voltage (for example, a ground potential VSS) is cut off, the match line is held at the precharged voltage.
Further, when the stored data is the “Don't care’ state or the inputted data is the MASK’ state, connection of the match line ML and the discharge line DCL is cut off, so that the match line is held at the precharge voltage like the match case.
Furthermore, when both the data are different from each other, namely, when both the data do not match with each other, since a current path is formed by making one of the stacked transistors T3, T4 or the stacked transistors T5, T6 conductive, the match line ML and the discharge line DCL short-circuit so that the match line ML is discharged toward the ground potential VSS.
The comparison result is determined by discriminating voltage change of the match line ML due to the above operation using a match line sense amplifier (not shown).
FIG. 26 is a truth table collectively representing the above search operations.
U.S. Pat. No. 6,343,029 (hereinafter, called ‘Literature 2’) describes another example of the CAM cell structure. A main portion of a cell structure and an array structure shown in FIG. 1 in Literature 2 is shown in FIG. 22. In FIG. 22, transistors acting in the same manner as those in FIG. 21 are allocated with same symbols in order to assist understanding.
The cell is for comparing data held in storage circuits CST1, CST2 with data inputted via search lines SL1 and SL2 in a comparator CCP, and it has two features described below.
A first feature lies in that a signal corresponding to comparison result is generated according to charge-sharing operation using a match line ML and a common source-line CSL arranged in parallel.
A second feature lies in that connecting lines of transistors constituting the comparator CCP is different from those in the cell shown in FIG. 21. That is, the transistor T4 connected to the storage node N1 is connected to the match line ML and the transistor T3 connected to the search line SL2 is connected to a common source-line CSL, respectively.
Similarly, the transistor T6 connected to the storage node N2 is connected to the match line ML, and the transistor T5 connected to the search line SL1 is connected to the common source-line CSL, respectively. Incidentally, the comparator CCP can performs XNOR operation similar to that in the cell shown in FIG. 21 even if connections in the cell are different.
Next, the charge-sharing operation in the search operation will be explained.
In a standby state, first, the match line ML is precharged to a high voltage VPCH and the common source-line CSL is precharged to the ground potential VSS respectively by making a PMOS (P-channel MOS) transistor THP and an NMOS transistor TL conductive.
When a search operation starts, first, the transistors THP and TL are put in a cut-off state and the match line ML and the common source-line CSL are put in a floating state by driving precharge enable signals PREB and PRE.
Next, search key is inputted via the search lines SL1 and SL2. Here, when the entry and the search key are the same, since connection of the match line ML and the common source-line CSL is cut off, the match line ML is held at the precharge voltage VPCH.
On the other hand, when the entry and the search key are different from each other, a current path is formed in the comparator CCP like the cell shown in FIG. 21, so that the match line ML and the common source-line CSL are caused to short-circuit. Therefore, charge stored in a parasitic capacitance CM of the match line ML is divided to the parasitic capacitance CM and a parasitic capacitance CC of the common source-line CSL, so that a voltage of the match line ML lowers.
Finally, the comparison result of data is determined by discriminating voltage change of the match line ML. In such an operation, when the parasitic capacitance CM and the parasitic capacitance CC are the same, a voltage of the match line ML after short-circuiting becomes an intermediate voltage VPCH/2 between the precharge voltage VPCH and the ground potential VSS.
In the structure shown in FIG. 22, therefore, since a voltage amplitude in the match line is small as compared with a case that the common source-line CSL is connected to the ground potential VSS like the structure shown in FIG. 21, power required for match line precharging is suppressed.
The CAM described in the above Literatures is a device which compares a plurality of stored data (hereinafter, called “entry”) and comparison data (hereinafter, called “search key”) with each other simultaneously, to determine whether or not the former and the latter are equal to each other or different from each other.
Therefore, a demand in communication equipment application such as a router or a switch where high speed in table search is required increases. However, table scale rapidly increases according to recent explosive growth of Internet, which is problematic regarding advance in large capacity of the TCAM.
As the result obtained when the inventors of the present invention examined the large capacity of the TCAM prior to making the present invention, the inventors has found out that consideration about advance in high integration and advance in low power consumption has not been made sufficiently in the memory cell structure shown in FIG. 21 and FIG. 22.
Regarding the first advance in high integration, it is effective to make a capacitor three-dimensional and introduce a commodity DRAM fabricating technique using a self-aligned process in order to further reduce a memory cell area.
However, since the memory cell shown in FIG. 21 includes a large number of elements and a large number of signals, there is a possibility that it is difficult to realize a layout and a structure of a regular memory array such as the commodity DRAM and it is difficult to introduce the self-aligned process.
Further, as seen in the storage nodes N1 and N2, since a structure for connecting the gate electrode and the source or drain electrode of the transistor, which is not included in the commodity DRAM, is required in the memory cell, matching with manufacturing steps for the commodity DRAM can not be achieved, which may require development of a new manufacturing technique.
Regarding the second advance in low power consumption, the charge-sharing operation based upon the structure shown in FIG. 22 is effective for suppressing precharge power in the match line. In a structure of the comparator CCP shown in FIG. 22, however, influence of noises due to a coupling capacitance between wires which may be problematic in a commodity DRAM using extremely fine machining becomes large, which may result in increase in time required for comparison operation.
FIG. 23 shows a main portion of a cell structure and an array structure of CAM examined in detail prior to making the present invention about this problem.
FIG. 23 is an equivalent circuit model obtained by considering a coupling capacitance in the memory cell CMC shown in FIG. 22, where coupling capacitances CSC1, CSC2 are inserted between the search lines SL1, SL2 and the common source-line CSL, and coupling capacitances CNMC1, CNMC2 are inserted between the storage nodes N1, N2 and the match line ML.
FIG. 24 and FIG. 25 show one example of a search operation timing in the structure shown in FIG. 23. Here, it is assumed that the memory cell CMC reserves the entry ‘1’ using the storage circuits CST1, CST2.
In this case, a logical value of the storage node is (N1, N2)=(1, 0), and the storage node N1 is held at the external power supply VDD, while the storage node N2 is held at the ground potential VSS. Accordingly, the transistor T4 is made conductive, while the transistor T6 is in a cut-off state.
Further, the reference voltage VR is a reference voltage for discriminating a voltage on the match line. Furthermore, the VSIGC is a voltage difference between a match line voltage required for accurate discrimination and the reference voltage VR, and it is hereinafter called “comparison signal voltage”.
In the beginning, search operation timing when the held data and the input data match with each other will be explained with reference to FIG. 24.
First, in a standby state, by driving a precharge enable signal PREB and a precharge enable signal PRE to the ground potential VSS and the external power supply VDD respectively, the transistors THP, TL are respectively made conductive to drive the match line ML and the common source-line CSL to the precharge voltage VPCH and the ground potential VSS respectively.
When the search operation starts, by driving the precharge enable signal PREB put in the ground potential VSS and the precharge enable signal PRE put in the external power supply to the ground potential VSS, respectively, each of the transistors THP, TL are put in an OFF state, and the match line ML and the common source-line CSL are put in a floating state.
Subsequently, search key is inputted through the search line. When the data of the search key compared with the stored data in the memory cell CMC is ‘1’, since the logical value of the search line is (SL1, SL2)=(1,0), the search line SL1 put in the ground potential VSS is driven to the external power supply VDD and the search line SL2 is held at the ground potential VSS.
Here, since the search line SL1 is coupled to the common source-line CSL via the parasitic capacitance CSC1, a voltage of the common source-line CSL rises according to activation of the search line SL1. Such a voltage rising due to fluctuation of the search line voltage is hereinafter called “search-line noise”.
Incidentally, though omitted in FIG. 23, since actual search key is data constituted of a plurality of bits, and a plurality of memory cells is connected to one match line, so that search-line noises are superimposed when a plurality of search lines are simultaneously driven.
Further, when data ‘X’ is inputted at the TCAM, a corresponding search line pair is held at the ground potential VSS. Accordingly, the capacitance of the search-line noise VNC shown in FIG. 24 becomes a value corresponding to a data pattern of the search key, namely, the number of search lines to be driven.
On the other hand, though the match line ML is connected to the storage nodes N1, N2 via the coupling capacitances CNMC1, CNMC2, respectively, voltages of the storage nodes are held, so that the match line ML is held at the precharge voltage VPCH.
Now, the transistor T5 in the memory cell CMC11 is made conductive by inputting of the search key, but no current flows on the side of the storage node N2 in the comparator CP because the transistor T6 is in the cut-off state.
Further, since the transistor T3 is in the cut-off state, no current also flows to the storage node N1. That is, the comparator CP in the memory cell CMC11 is in a matched state.
Accordingly, since the match line ML is held at the precharge voltage VPCH, match determination is made by detecting that a positive comparison signal VSIGC relative to the reference voltage VR is generated in the match line ML utilizing any method.
Next, a search operation when the search key and the entry are different from each other will be explained with reference to FIG. 25. An operation for making the match line ML and the common source-line CSL in a floating state and then inputting the search key is as describe above.
A search operation when the entry in the memory cell CMC and data to be compared are ‘0’ will be described below.
In this case, since the logical value in the search line is (SL1, SL2)=(0, 1), the search line SL1 is held at the ground potential VSS, while the search line SL2 put in the ground potential VSS is driven to the external power supply VDD.
Here, since the search line SL2 is coupled to the common source-line CSL via the parasitic capacitance CSC2, the voltage on the common source-line CSL rises according to activation of the search line SL2 like the case shown in FIG. 24.
Now, when the search key is inputted, the transistor T3 in the memory cell MC11 is made conductive, so that a current path is formed on the side of the storage node N1 in the comparator CCP and thereby the match line ML and the common source-line are short-circuited to each other.
That is, the match line ML driven to the precharge voltage VPCH is discharged toward an intermediate voltage VM and the common source-line CSL precharged to the ground potential VSS is charged toward the intermediate voltage VM.
Therefore, it is determined that the comparison result shows unmatch by discriminating that the voltage in the match line ML has been below the reference voltage VR and a negative comparison signal voltage—VSIGC relative to the reference voltage has been generated utilizing any method. Finally, by driving the search line SL2 put in the external power supply VDD to the ground potential VSS and driving the precharge enable signal PREB put in the external power supply VDD and the precharge enable signal PRE put in the ground potential VSS to the ground potential VSS and the external power supply VDD, respectively, to precharge the match line ML and the common source-line CSL respectively, the search operation is terminated.
Incidentally, t1 indicates a time elapsing from driving of the search line to generation of the negative comparison signal voltage—VSIGC, and it is hereinafter called “search time”. In FIG. 25, a match line waveform where other memory cells connected to the match line ML are put in a matched state is shown for explaining an operation timing under the worst conditions.
However, when other memory cells are in an unmatched state, since the match line and the common source-line CSL are short-circuited by current path formed in a plurality of memory cells, it is apparent that they are changed to the intermediate voltage VM faster than the waveform shown in FIG. 25.
Further, when the coupling capacitances CSC1, CSC2, CNMC1, CNMC2 are the same value, and load capacitances of the match line ML and the common source-line CSL are equal to each other, a voltage after the short-circuit becomes VPCH/2. However, it will be understood easily that the voltage after the short-circuit becomes a voltage VM higher than VPCH/2 according to the capacitance of the search-line noise.
From the above search operation, since a voltage at the source electrode (here, the common source-line CSL) rises due to the search-line noise so that the gate-source voltage becomes small and a threshold voltage further rises due to a substrate bias effect, a driving ability in the transistor T3, T5 in the memory cell CMC shown in FIG. 23 lowers.
Therefore, in the TCAM according to the structure shown in FIG. 23, a precharging power on the match line can be suppressed, but there is such a possibility that the search time t1 significantly increases due to the data pattern of the search key, which results in slowdown of the search operation.
An object of the present invention is to provide a layout of a memory cell and an internal node connection technique for applying a commodity DRAM fabricating technique for advance in high integration of a TDCAM cell.
Another object of the present invention is to provide a technique for avoiding increase in a search time due to search-line noise in a charge-sharing system effective for advance in power consumption reduction in a match line.
The aforesaid and other objects, and a novel feature of the present invention will be apparent from the description in the text and the accompanying drawings.